1. Field of the Invention
The present invention relates generally to microcomputers. More particularly, the present invention relates to methods and apparatus for carrying out debugging operations on microcomputers.
2. Discussion of the Related Art
System-on-chip devices (SOCs), generally microcomputers, are well-known. These devices generally include a processor, one or more modules, bus interfaces, memory devices, and one or more system busses for communicating information. When designing, testing, and checking the microcomputer, it is necessary to operate the microcomputer in a mode so that problems with programs executing on the microcomputer can be identified and corrected. This process of problem identification and correction is known as xe2x80x9cdebuggingxe2x80x9d. Because multiple modules and their communications occur internally to the chip, access to this information to this information is generally difficult when problems occur in software or hardware. Thus, debugging on these systems is not straightforward. As a result of development of these SOCs, specialized debugging systems have been developed to monitor performance and trace information on the chip. Such systems typically include dedicated hardware or software such as a debug tool and debug software which accesses a processor through serial communications.
However, debugging an SOC generally involves intrusively monitoring one or more processor registers or memory locations. Accesses to memory locations are sometimes destructive, and data access to a location being read from a debugging tool may impede processor performance. Similarly, accesses are generally performed over a system bus to the processor, memory, or other module, and may reduce available bandwidth over the system bus for performing general operations. Some debugging systems do not perform at the same clock speed as that of the processor, and it may be necessary to slow the performance of the processor to enable use of debugging features such as obtaining trace information. By slowing or pausing the processor, some types of error may not be reproduced, and thus cannot be detected or corrected. Further, accurate information may not be available altogether due to a high speed of the processor; information may be skewed or missing.
Some systems include one or more dedicated functional units within the SOC that are dedicated to debugging the processor, sometimes referred to as a debug unit or module. However, these units affect the operation of the processor when obtaining information such as trace information. These devices typically function at a lower speed than the processor, and thus affect processor operations when they access processor data. The debug system relies upon running debug code on the target processor itself, and this code is usually built into the debugee. Thus, the presence of the debug code is intrusive in terms of memory layout, and instruction stream disruption.
Other debugging systems referred to as in-circuit emulators (ICEs) match on-chip hardware and are connected to it. Thus, on-chip connections are mapped onto the emulator and are accessible on the emulator which is designed specifically for the chip to be tested. However, emulators are prohibitively expensive for some applications because they are specially-developed hardware, and do not successfully match all on-chip speeds or communications. Thus, emulator systems are inadequate. Further, these systems generally transfer information over the system bus, and therefore necessarily impact processor performance. These ICEs generally use a proprietary communication interface that can only interface with external debug equipment from the same manufacturer.
Another technique for troubleshooting includes using a Logic State analyzer (LSA) which is a device connected to pins of the integrated circuit that monitors the state of all off-chip communications. LSA devices are generally expensive devices, and do not allow access to pin information inside the chip.
Conventionally, there are two main types of development system architectures that may be used to debug a microcomputer. FIG. 1 illustrates a first type of debugging system. The system includes a target processor board 10. The target processor board 10 has a target processor 12 disposed thereon. Target processor 12 is the microcomputer that is being debugged by the debugging system. A monitor ROM 14 coupled to target processor 12 via data link 16 is also provided. A serial port interface 18 is provide to couple target processor 12 via data link 20 with host computer 22 via data link 24. Host computer 22 runs a software backplane/operating system 26 that allows a software debugger system 28 to access target processor 12. In the system illustrated in FIG. 1, the target processor 12 may have minimal or no debug features. Most of the tools necessary for debugging the operation of target processor 12 are contained in debugger software system 28.
The system of FIG. 1 is somewhat limited in the types of debugging operations that can be performed. Since a serial port is used to communicate between the target processor 12 and the host computer 22, the system is typically not capable of controlling the CPU directly to, for example, cause target processor 12 to boot from software executing on host computer 22. In addition, the debugging system of FIG. 1 can be intrusive since the system relies upon executing code on the target processor 12 itself. Thus, host computer 22 can and does actually disrupt the execution of code on target processor 12. Since the host computer 22 actually perturbs operation of target processor 12 during debugging operations, the results of the debugging operations may be subject to some uncertainty since the presence of the debugging system itself may alter the behavior of the target processor.
FIG. 2 illustrates another conventional debugging system. In the debugging system of FIG. 2, target processor 12 is connected to a debug adaptor 30 via a debug link 32. A host computer 22 runs a software backplane/operating system 26 that supports debugger system 28. Host computer 22 communicates with debug adapter 30 via bidirectional data link 34. Debug adapter 30 is xe2x80x9cintelligentxe2x80x9d. It includes a CPU 36 and a random access memory 38 that executes adapter software to translate between the communication protocol of the debug link 32 and the communication protocol of the data link 34. Debug data link 32 may be, for example, an Ethernet connection or a PCI bus.
Optionally, external hardware such as a logic analyzer 40 may be provided that can supply a triggering signal to target processor 12 via trigger-in data link 42 and receive a trigger signal from target processor 12 via trigger-out data link 44.
The debug system of FIG. 2 does not require additional off-chip hardware, to interface the target processor to the debugging system, as is needed in the system of FIG. 1. This allows production target processors 12 to be debugged without requiring that they be combined with additional components prior to connection to the debugging system extra components. In addition, enhanced debugging features can be provided because of the inclusion of debug adaptor 30 in the system. However, the debugging system of FIG. 2 still suffers from at least the limitation of being intrusive in that the debugging software may still perturb operation of target processor 12.
According to one aspect of the invention, there is provided a computer system comprising at least one central processing unit, a memory unit coupled to the at least one central processing unit, a set of watchpoints defined in the computer system, each watchpoint in the set of watchpoints comprising a programmable precondition register that stores a set of precondition codes, wherein the set of precondition codes is identical for each watchpoint in the set of watchpoints, a programmable action register that stores a set of action codes, wherein the set of action codes is identical for each watchpoint in the set of watchpoints, and a first comparator, having inputs coupled to the precondition register, that compares at least one precondition code in the set of precondition codes with a first data value in the computer system and provides a signal to the action register in response thereto.
According to another aspect of the invention, the comparator provides the signal to the action register if the first data value in the computer system satisfies the precondition code.
According to another aspect of the invention, the computer system responds to the signal provided to the action register and generates a signal, determined by the action code, indicating that the watchpoint has been triggered.
According to another aspect of the invention the computer system includes hardware and software that selects which precondition codes in the set of precondition codes are active for a particular watchpoint in the set of watchpoints.
According to another aspect of the invention, the computer system includes hardware and software that selects which action codes in the set of action codes are active for a particular watchpoint in the set of watchpoints.
According to another aspect of the invention, the set of watchpoints includes types of watchpoints for operand addresses, instruction values, instruction addresses, branches, breakpoint instructions, and print instructions.
According to another aspect of the invention, each watchpoint further comprises a programmable match register that stores at least one match code, wherein the match code stored depends on the type of watchpoint.
According to another aspect of the invention, the computer system further comprises a second comparator, having inputs coupled to the first comparator, that responds to the first comparator, and compares the at least one match code with a second data value in the computer system and provides the signal to the action register in response thereto.
According to another aspect of the invention, the match code includes at least one of an address range, a data value, a data mask, an instruction value, an instruction mask, a branch type, and a signal external to the at least one central processing unit.
According to another aspect of the invention, the second comparator provides the signal to the action register if the second data value in the computer system matches the match code.
According to another aspect of the invention, the set of precondition codes includes a basic enable code, an address space identifier enable code, an address space identifier code a latch enable code, a latch identifier code, an event counter enable code, an event counter identifier code, an Instruction Set Architecture (ISA) mode enable code, and a CPU supervisor mode selection code.
According to another aspect of the invention, the set of action codes includes an exception enable code, an event count decrement enable code, an event counter identifier code, a latch alter code, a latch identifier code, a performance counter increment enable code, a reset all performance counters code, a performance counter identifier code, a trace enable code, a trace message type code, an enable trace time stamp code, a trigger out enable code, and an interrupt enable code.
According to another aspect of the invention, the computer system is implemented on a single integrated circuit chip.
According to another aspect of the invention, each watchpoint comprises a programmable match register that stores at least one match code, wherein the match code stored depends on the type of watchpoint and wherein the precondition register, the match register, and the action register occupy respective memory locations in the memory unit.
According to another aspect of the invention, there is provided a computer system comprising at least one central processing unit, a memory unit coupled to the at least one central processing unit, a set of watchpoints defined in the computer system, each watchpoint in the set of watchpoints comprising a first programmable storage means for storing at least one precondition code that is identical for each watchpoint in the set of watchpoints, a second programmable storage means for storing at least one action code that is identical for each watchpoint in the set of watchpoints, and a comparator, having inputs responsive to the first programmable storage means, that compares the at least one precondition code with a data value in the computer system and provides a signal to the second programmable storage means in response thereto.
According to another aspect of the invention, there is provided a method of triggering a watchpoint in a computer system comprising at least one central processing unit and a memory unit coupled to the at least one central processing unit, the method comprising the steps of defining a set of watchpoints in the computer system by defining a set of precondition registers and a set of action registers, storing a set of precondition codes in a precondition register, wherein the set of precondition codes is identical for each watchpoint in the set of watchpoints, storing a set of action codes in an action register, wherein the set of action codes is identical for each watchpoint in the set of watchpoints, comparing at least one precondition code in the set of precondition codes with a first data value in the computer system and providing a signal to the action register in response thereto.
According to another aspect of the invention, the step of comparing includes the step of providing the signal to the action register if the first data value in the computer system satisfies the precondition code.
According to another aspect of the invention, the method comprises the step of selecting which precondition codes in the set of precondition codes are active for a particular watchpoint in the set of watchpoints.
According to another aspect of the invention, the method comprises the step of selecting which action codes in the set of action codes are active for a particular watchpoint in the set of watchpoints.
According to another aspect of the invention the set of watchpoints includes types of watchpoints for operand addresses, instruction values, instruction addresses, branches, breakpoint instructions, and print instructions.
According to another aspect of the invention, the method comprises the step of defining a programmable match register and storing an at least one match code in the match register, wherein the match code depends on the type of watchpoint.
According to another aspect of the invention, the method comprises the step of comparing, after the at least one precondition code has been satisfied, the-at least one match code with a second data value in the computer system.
According to another aspect of the invention, the signal is provided to the action register if the second data value matches the match code.
According to another aspect of the invention, the set of precondition codes includes a basic enable code, an address space identifier enable code, an address space identifier code, a latch enable code, a latch identifier code, an event counter enable code, an event counter identifier code, an ISA mode enable code, and a CPU supervisor mode selection code.
According to another aspect of the invention, the computer system comprises a set of action codes including an exception enable code, an event count decrement enable code, an event counter identifier code, a latch alter code, a latch identifier code, a performance counter increment enable code, a reset all performance counters code, a performance counter identifier code, a trace enable code, a trace message type code, an enable trace time stamp code, a trigger out enable code, and an interrupt enable code.
According to another aspect of the invention, the computer system further comprises the step of defining the precondition register, the match register, and the action register in respective memory locations in the memory unit.
According to another aspect of the invention there is provided a method of filtering debugging data in a computer system comprising at least one central processing unit and a memory unit coupled to the at least one central processing unit, the method comprising the steps of defining a set of watchpoints in the computer system by defining a set of precondition registers and a set of action registers, defining a set of identical precondition codes to be applied to each watchpoint in the set of watchpoints, defining a set of identical action codes to be applied to each watchpoint in the set of watchpoints, storing the set of precondition codes in each precondition register in the set of precondition registers, storing the set of action codes in each action register in the set of action registers, selecting which precondition codes in the set of precondition codes are to be active for a particular watchpoint, selecting which action code in the set of action codes are to be active for a particular watchpoint, operating the computer system so as to execute a program, comparing the debugging data in the computer system with the active precondition codes for a particular watchpoint, sending a signal to the action register for the particular watchpoint when the debugging data in the computer system satisfies the active precondition codes for the particular watchpoint, and causing the computer to respond to the active action codes for the particular watchpoint.
According to another aspect of the invention, the set of watchpoints includes types of watchpoints for operand addresses, instruction values, instruction addresses, branches, breakpoint instructions, and print instructions.
According to another aspect of the invention, the set of precondition codes includes a basic enable code, an address space identifier enable code, an address space identifier code, a latch enable code, a latch identifier code, an event counter enable code, an even counter identifier code, an ISA mode enable code, and a CPU supervisor mode selection code.
According to another aspect of the invention, the set of action codes includes an exception enable code, an event count decrement enable code, an event counter identifier code, a latch alter code, a latch identifier code, a performance counter increment enable code, a reset all performance counters code, a performance counter identifier code, a trace enable code, a trace message type code, an enable trace time stamp code, a trigger out enable code, and an interrupt enable code.
According to another aspect of the invention, the method comprises the step of defining a programmable match register and storing an at least one match code in the match register, wherein the match code depends on the type of watchpoint.
According to another aspect of the invention, the method comprises the step of comparing, after the at least one precondition code has been satisfied, the at least one match code with a second data value in the computer system.
According to another aspect of the invention, the signal is provided to the action register if the second data value matches the match code.
According to another aspect of the invention, the match code includes at least one of an address range, a data value, a data mask, an instruction value, and instruction mask, a branch type, and a signal external to the at least one central processing unit.
According to another aspect of the present invention, the method comprises the step of defining the precondition register, the match register, and the action register in respective memory locations in the memory unit.
According to another aspect of the invention, there is provided a computer system comprising at least one central processing unit, a memory unit coupled to the at least one central processing unit, a set of watchpoints defined in the computer system, each watchpoint in the set of watchpoints comprising a programmable precondition register and a programmable action register, a set of latches, and selection circuitry that selects one latch in the set of latches to couple an output of an action register to an input of the selected latch.
According to another aspect of the invention, the selection circuitry comprises a demultiplexer having an input coupled to the output of the action register and a plurality of outputs each respectively coupled to an input of each latch in the set of latches.
According to another aspect of the invention, the selection circuitry comprises a multiplexer having a plurality of inputs each respectively coupled to an output of each latch in the set of latches and an input coupled to a precondition register.
According to another aspect of the invention, the computer system further comprises a set of demultiplexers corresponding to the set of watchpoints, each demultiplexer in the set of demultiplexers having an input respectively coupled to an output of a respective action register in the set of watchpoints, each demultiplexer in the set of demultiplexers having a plurality of outputs respectively coupled to an input of each latch in the set of latches.
According to another aspect of the invention, the computer system further comprises a set of multiplexers corresponding to the set of watchpoints, each multiplexer in the set of multiplexers having a plurality of inputs respectively coupled to an output of each latch in the set of latches, each multiplexer in the set of multiplexers having an output coupled to an input of a respective precondition register in the set of watchpoints.
According to another aspect of the invention, the computer system further comprises a control register respectively associated with a latch in the set of latches, the control register having a state, responsive to a signal external to the computer system, that sets or resets the latch.
According to another aspect of the invention, the computer system is implemented on a single integrated circuit chip.
According to another aspect of the invention, the demultiplexer includes a select output, responsive to a state of the action register, that controls the demultiplexer to select an input of one latch in the set of latches.
According to another aspect of the invention, the multiplexer includes a select input, responsive to a state of the precondition register, that controls the multiplexer to select an output of one latch in the set of latches.
According to another aspect of the invention, each multiplexer has a select input, responsive to a state of a respective precondition register, that controls each multiplexer to select an output of one latch in the set of latches.
According to another aspect of the invention, each demultiplexer has a select output, responsive to a state of a respective action register, that controls the demultiplexer to select an input of one latch in the set of latches.
According to another aspect of the invention, the precondition register stores a set of precondition codes, wherein the set of precondition codes is identical for each watchpoint in the set of watchpoints.
According to another aspect of the invention, the action register stores a set of action codes, wherein the set of action codes is identical for each watchpoint in the set of watchpoints.
According to another aspect of the invention, the computer system includes hardware and software that selects which precondition codes in the set of precondition codes are active for a particular watchpoint in the set of watchpoints.
According to another aspect of the invention, the computer system includes hardware and software that selects which action codes in the set of action codes are active for a particular watchpoint in the set of watchpoints.
According to another aspect of the invention, the set of watchpoints includes types of watchpoints for operand addresses, instruction values, instruction addresses, branches, breakpoint instructions, and print instructions.
According to another aspect of the invention, each watchpoint further comprises a programmable match register that stores at least one match code, wherein the match code stored depends on the type of watchpoint.
According to another aspect of the invention, the match code includes at least one of an address range, a data value, a data mask, an instruction value, an instruction mask, and a branch type.
According to another aspect of the invention, the set of precondition codes includes a basic enable code, an address space identifier enable code, an address space identifier code, a latch enable code, a latch identifier code, an event counter enable code, an even counter identifier code, an ISA mode enable code, and a CPU supervisor mode selection code.
According to another aspect of the invention, the set of action codes includes an exception enable code, an event count decrement enable code, an event counter identifier code, a latch alter code, a latch identifier code, a performance counter increment enable code, a reset all performance counters code, a performance counter identifier code, a trace enable code, a trace message type code, an enable trace time stamp code, a trigger out enable code, and an interrupt enable code.
According to another aspect of the invention there is provided a computer system, comprising, at least one central processing unit, a memory unit coupled to the at least one central processing unit, a set of watchpoints defined in the computer system, and means for linking one watchpoint in the set of watchpoints with at least one other watchpoint in the set of watchpoints, wherein the means for linking is programmable.
According to another aspect of the invention, the means for linking includes, associated with each watchpoint, a programmable precondition register that stores a set of precondition codes, wherein the set of precondition codes is identical for each watchpoint in the set of watchpoints and a programmable action register that stores a set of action codes, wherein the set of action codes is identical for each watchpoint in the set of watchpoints.
According to another aspect of the invention, the means for linking further comprises a latch.
According to another aspect of the invention, the latch is coupled between an output of an action register associated with one watchpoint in the set of watchpoints and an input of every input of every other precondition register in the set of watchpoints.
According to another aspect of the invention, there is provided a method of operating a computer system comprising at least one central processing unit and a memory unit coupled to the at least one central processing unit, the method comprising the steps of defining a set of watchpoints in the computer system by defining a set of precondition registers and a set of action registers, defining a set of identical precondition codes to be applied to each watchpoint in the set of watchpoints, defining a set of identical action codes to be applied to each watchpoint in the set of watchpoints, storing the set of precondition codes in each precondition register in the set of precondition registers, storing the set of action codes in each action register in the set of action registers, selecting which precondition codes in the set of precondition codes are to be active for a particular watchpoint, selecting which action code in the set of action codes are to be active for a particular watchpoint, operating the computer system so as to execute a program, comparing the debugging data in the computer system with the active precondition codes for a particular watchpoint, sending a signal to the action register for the particular watchpoint when the debugging data in the computer system satisfies the active precondition codes for the particular watchpoint, and wherein the computer system responds to the active action code by generating a trigger signal and the computer system further responds to the trigger signal by setting or clearing a latch in response to a state of the trigger signal.
According to another aspect of the invention, the computer system comprises a set of latches and the method further comprises the step of selecting a latch in the set of latches to respond to the trigger signal.
According to another aspect of the invention, the method further comprises the step of providing an output signal from the latch to each precondition register in the set of watchpoints.
According to another aspect of the invention, the method further comprises the step of selecting a precondition register to respond to the output signal from the latch.
According to another aspect of the invention, the set of watchpoints includes types of watchpoints for operand addresses, instruction values, instruction addresses, branches, breakpoint instructions, and print instructions.
According to another aspect of the invention, the set of precondition codes includes a basic enable code, an address space identifier enable code, an address space identifier code, a latch enable code, a latch identifier code, an event counter enable code, an even counter code, an Institution Set Architecture (ISA) mode enable code, and a CPU supervisor mode selection code.
According to another aspect of the invention, the set of action codes includes an exception enable code, an event count decrement enable code, an event counter identifier code, a latch alter code, a latch identifier code, a performance counter increment enable code, a reset all performance counters code, a performance counter identifier code, a trace enable code, a trace message type code, an enable trace time stamp code, a trigger out enable code, and an interrupt enable code.
According to another aspect of the invention, the method comprises the step of defining a programmable match register and storing at least one match code in the match register, wherein the match code depends on the type of watchpoint.
According to another aspect of the invention, the method further comprises the step of comparing, after the at least one precondition code has been satisfied, the at least one match code with a second data value in the computer system.
According to another aspect of the invention, the signal is provided to the action register if the second data value matches the match code.
According to another aspect of the invention, the method further comprises the step of defining the precondition register, the match register, and the action register in respective memory locations in the memory unit.
According to another aspect of the invention, there is provided a computer system comprising at least one central processing unit, a memory unit coupled to the at least one central processing unit, a set of watchpoints defined in the computer system, each watchpoint in the set of watchpoints comprising a programmable precondition register that stores a set of precondition codes, wherein the set of precondition codes is identical for each watchpoint in the set of watchpoints, a programmable action register that stores a set of action codes, wherein the set of action codes is identical for each watchpoint in the set of watchpoints, a set of latches, each latch having an input and an output, and circuitry that couples at least one latch in the set of latches to at least two watchpoints in the set of watchpoints so that there is a predetermined relationship between triggering of the at least two watchpoints.
According to another aspect of the invention, the predetermined relationship is defined by which precondition codes in the set of precondition codes are active and by which action codes in the set of action codes are active.
According to another aspect of the invention, the predetermined relationship is an AND function.
According to another aspect of the invention, the predetermined relationship is an OR function.
According to another aspect of the invention, a first one of the at least two watchpoints is triggered when the first watchpoint is triggered and when a second one of the at least two watchpoints is also triggered.
According to another aspect of the invention, an action register of a first watchpoint is coupled to a set input of the latch and an action register of a second watchpoint is coupled to a reset input of the latch and further comprising a third watchpoint having a precondition register coupled to an output of the latch so that triggering of the first watchpoint sets the latch to enable the third watchpoint and triggering of the second watchpoint resets the latch to disable the third watchpoint.
According to another aspect of the invention, an action register of a first watchpoint is coupled to a set input of the latch and an action register of a second watchpoint is coupled to a reset input of the latch and a precondition register of the second watchpoint is coupled to an output of the latch so that triggering of the first watchpoint sets the latch to enable the second watchpoint and triggering of the second watchpoint resets the latch to disable the second watchpoint.
According to another aspect of the invention, a respective action register for first number of watchpoints in the set of watchpoints is coupled to a set input of the latch and a respective action register of a second number of watchpoints in the set of watchpoints is coupled to a reset input of the latch and further comprising another watchpoint having a precondition register coupled to an output of the latch so that triggering of any of the first number of watchpoints sets the latch to enable the another watchpoint and triggering of any of the second number of watchpoints resets the latch to disable the third watchpoint.
According to another aspect of the invention, there is provided a method of filtering debugging data in a computer system comprising at least one central processing unit and a memory unit coupled to the at least one central processing unit, the method comprising the steps of defining a set of at least three watchpoints in the computer system by defining a set of precondition registers and a set of action registers for each watchpoint, defining a set of identical precondition codes to be applied to each watchpoint in the set of watchpoints, defining a set of identical action codes to be applied to each watchpoint in the set of watchpoints, storing the set of precondition codes in each precondition register in the set of precondition registers, storing the set of action codes in each action register in the set of action registers, selecting which precondition codes in the set of precondition codes are to be active for each of the at least three watchpoints, selecting which action codes in the set of action codes are to be active for each of the at least three watchpoints so that the first and second watchpoints activate a precondition code in the precondition register of the third watchpoint, operating the computer system so as to execute a program, comparing the debugging data in the computer system with the active precondition codes for each of the at least three watchpoints, and triggering one of the first and second watchpoints when the debugging data in the computer system satisfies the active precondition codes for the first or second watchpoints and triggering the third watchpoint in response to triggering of one of the first and second watchpoints.
According to another aspect of the invention, the set of watchpoints includes types of watchpoints for operand addresses, instruction values, instruction addresses, branches, breakpoint instructions, and print instructions.
According to another aspect of the invention, the set of precondition codes includes a basic enable code, an address space identifier enable code, an address space identifier code, a latch enable code, a latch identifier code, an event counter enable code, an event counter identifier code, an ISA mode enable code, and a CPU supervisor mode selection code.
According to another aspect of the invention, the set of action codes includes an exception enable code, an event count decrement enable code, an event counter identifier code, a latch alter code, a latch identifier code, a performance counter increment enable code, a reset all performance counters code, a performance counter identifier code, a trace enable code, a trace message type code, an enable trace time stamp code, a trigger out enable code, and an interrupt enable code.
According to another aspect of the invention, the method comprises the step of defining a programmable match register and storing an at least one match code in the match register, wherein the match code depends on the type of watchpoint.
According to another aspect of the invention, the method further comprises the step of comparing, after the at least one precondition code has been satisfied, the at least one match code with a second data value in the computer system.
According to another aspect of the invention, the signal is provided to the action register if the second data value matches the match code.
According to another aspect of the invention, the method further comprises the step of defining the precondition register, the match register, and the action register in respective memory locations in the memory unit.